[][src]Module core::arch::mips64

🔬 This is a nightly-only experimental API. (stdsimd #27731)
This is supported on MIPS-64 only.

Platform-specific intrinsics for the mips64 platform.

See the module documentation for more details.

Structs

v16i8ExperimentalMIPS-64
v16u8ExperimentalMIPS-64
v2f64ExperimentalMIPS-64
v2i64ExperimentalMIPS-64
v2u64ExperimentalMIPS-64
v4f32ExperimentalMIPS-64
v4i32ExperimentalMIPS-64
v4u32ExperimentalMIPS-64
v8i16ExperimentalMIPS-64
v8u16ExperimentalMIPS-64

Functions

__msa_add_a_bExperimentalMIPS-64 and msa

Vector Add Absolute Values.

__msa_add_a_dExperimentalMIPS-64 and msa

Vector Add Absolute Values

__msa_add_a_hExperimentalMIPS-64 and msa

Vector Add Absolute Values

__msa_add_a_wExperimentalMIPS-64 and msa

Vector Add Absolute Values

__msa_adds_a_bExperimentalMIPS-64 and msa

Signed Saturated Vector Saturated Add of Absolute Values

__msa_adds_a_dExperimentalMIPS-64 and msa

Vector Saturated Add of Absolute Values

__msa_adds_a_hExperimentalMIPS-64 and msa

Vector Saturated Add of Absolute Values

__msa_adds_a_wExperimentalMIPS-64 and msa

Vector Saturated Add of Absolute Values

__msa_adds_s_bExperimentalMIPS-64 and msa

Vector Signed Saturated Add of Signed Values

__msa_adds_s_dExperimentalMIPS-64 and msa

Vector Signed Saturated Add of Signed Values

__msa_adds_s_hExperimentalMIPS-64 and msa

Vector Signed Saturated Add of Signed Values

__msa_adds_s_wExperimentalMIPS-64 and msa

Vector Signed Saturated Add of Signed Values

__msa_adds_u_bExperimentalMIPS-64 and msa

Vector Unsigned Saturated Add of Unsigned Values

__msa_adds_u_dExperimentalMIPS-64 and msa

Vector Unsigned Saturated Add of Unsigned Values

__msa_adds_u_hExperimentalMIPS-64 and msa

Vector Unsigned Saturated Add of Unsigned Values

__msa_adds_u_wExperimentalMIPS-64 and msa

Vector Unsigned Saturated Add of Unsigned Values

__msa_addv_bExperimentalMIPS-64 and msa

Vector Add

__msa_addv_dExperimentalMIPS-64 and msa

Vector Add

__msa_addv_hExperimentalMIPS-64 and msa

Vector Add

__msa_addv_wExperimentalMIPS-64 and msa

Vector Add

__msa_addvi_bExperimentalMIPS-64 and msa

Immediate Add

__msa_addvi_dExperimentalMIPS-64 and msa

Immediate Add

__msa_addvi_hExperimentalMIPS-64 and msa

Immediate Add

__msa_addvi_wExperimentalMIPS-64 and msa

Immediate Add

__msa_and_vExperimentalMIPS-64 and msa

Vector Logical And

__msa_andi_bExperimentalMIPS-64 and msa

Immediate Logical And

__msa_asub_s_bExperimentalMIPS-64 and msa

Vector Absolute Values of Signed Subtract

__msa_asub_s_dExperimentalMIPS-64 and msa

Vector Absolute Values of Signed Subtract

__msa_asub_s_hExperimentalMIPS-64 and msa

Vector Absolute Values of Signed Subtract

__msa_asub_s_wExperimentalMIPS-64 and msa

Vector Absolute Values of Signed Subtract

__msa_asub_u_bExperimentalMIPS-64 and msa

Vector Absolute Values of Unsigned Subtract

__msa_asub_u_dExperimentalMIPS-64 and msa

Vector Absolute Values of Unsigned Subtract

__msa_asub_u_hExperimentalMIPS-64 and msa

Vector Absolute Values of Unsigned Subtract

__msa_asub_u_wExperimentalMIPS-64 and msa

Vector Absolute Values of Unsigned Subtract

__msa_ave_s_bExperimentalMIPS-64 and msa

Vector Signed Average

__msa_ave_s_dExperimentalMIPS-64 and msa

Vector Signed Average

__msa_ave_s_hExperimentalMIPS-64 and msa

Vector Signed Average

__msa_ave_s_wExperimentalMIPS-64 and msa

Vector Signed Average

__msa_ave_u_bExperimentalMIPS-64 and msa

Vector Unsigned Average

__msa_ave_u_dExperimentalMIPS-64 and msa

Vector Unsigned Average

__msa_ave_u_hExperimentalMIPS-64 and msa

Vector Unsigned Average

__msa_ave_u_wExperimentalMIPS-64 and msa

Vector Unsigned Average

__msa_aver_s_bExperimentalMIPS-64 and msa

Vector Signed Average Rounded

__msa_aver_s_dExperimentalMIPS-64 and msa

Vector Signed Average Rounded

__msa_aver_s_hExperimentalMIPS-64 and msa

Vector Signed Average Rounded

__msa_aver_s_wExperimentalMIPS-64 and msa

Vector Signed Average Rounded

__msa_aver_u_bExperimentalMIPS-64 and msa

Vector Unsigned Average Rounded

__msa_aver_u_dExperimentalMIPS-64 and msa

Vector Unsigned Average Rounded

__msa_aver_u_hExperimentalMIPS-64 and msa

Vector Unsigned Average Rounded

__msa_aver_u_wExperimentalMIPS-64 and msa

Vector Unsigned Average Rounded

__msa_bclr_bExperimentalMIPS-64 and msa

Vector Bit Clear

__msa_bclr_dExperimentalMIPS-64 and msa

Vector Bit Clear

__msa_bclr_hExperimentalMIPS-64 and msa

Vector Bit Clear

__msa_bclr_wExperimentalMIPS-64 and msa

Vector Bit Clear

__msa_bclri_bExperimentalMIPS-64 and msa

Immediate Bit Clear

__msa_bclri_dExperimentalMIPS-64 and msa

Immediate Bit Clear

__msa_bclri_hExperimentalMIPS-64 and msa

Immediate Bit Clear

__msa_bclri_wExperimentalMIPS-64 and msa

Immediate Bit Clear

__msa_binsl_bExperimentalMIPS-64 and msa

Vector Bit Insert Left

__msa_binsl_dExperimentalMIPS-64 and msa

Vector Bit Insert Left

__msa_binsl_hExperimentalMIPS-64 and msa

Vector Bit Insert Left

__msa_binsl_wExperimentalMIPS-64 and msa

Vector Bit Insert Left

__msa_binsli_bExperimentalMIPS-64 and msa

Immediate Bit Insert Left

__msa_binsli_dExperimentalMIPS-64 and msa

Immediate Bit Insert Left

__msa_binsli_hExperimentalMIPS-64 and msa

Immediate Bit Insert Left

__msa_binsli_wExperimentalMIPS-64 and msa

Immediate Bit Insert Left

__msa_binsr_bExperimentalMIPS-64 and msa

Vector Bit Insert Right

__msa_binsr_dExperimentalMIPS-64 and msa

Vector Bit Insert Right

__msa_binsr_hExperimentalMIPS-64 and msa

Vector Bit Insert Right

__msa_binsr_wExperimentalMIPS-64 and msa

Vector Bit Insert Right

__msa_binsri_bExperimentalMIPS-64 and msa

Immediate Bit Insert Right

__msa_binsri_dExperimentalMIPS-64 and msa

Immediate Bit Insert Right

__msa_binsri_hExperimentalMIPS-64 and msa

Immediate Bit Insert Right

__msa_binsri_wExperimentalMIPS-64 and msa

Immediate Bit Insert Right

__msa_bmnz_vExperimentalMIPS-64 and msa

Vector Bit Move If Not Zero

__msa_bmnzi_bExperimentalMIPS-64 and msa

Immediate Bit Move If Not Zero

__msa_bmz_vExperimentalMIPS-64 and msa

Vector Bit Move If Zero

__msa_bmzi_bExperimentalMIPS-64 and msa

Immediate Bit Move If Zero

__msa_bneg_bExperimentalMIPS-64 and msa

Vector Bit Negate

__msa_bneg_dExperimentalMIPS-64 and msa

Vector Bit Negate

__msa_bneg_hExperimentalMIPS-64 and msa

Vector Bit Negate

__msa_bneg_wExperimentalMIPS-64 and msa

Vector Bit Negate

__msa_bnegi_bExperimentalMIPS-64 and msa

Immediate Bit Negate

__msa_bnegi_dExperimentalMIPS-64 and msa

Immediate Bit Negate

__msa_bnegi_hExperimentalMIPS-64 and msa

Immediate Bit Negate

__msa_bnegi_wExperimentalMIPS-64 and msa

Immediate Bit Negate

__msa_bnz_bExperimentalMIPS-64 and msa

Immediate Branch If All Elements Are Not Zero

__msa_bnz_dExperimentalMIPS-64 and msa

Immediate Branch If All Elements Are Not Zero

__msa_bnz_hExperimentalMIPS-64 and msa

Immediate Branch If All Elements Are Not Zero

__msa_bnz_vExperimentalMIPS-64 and msa

Immediate Branch If Not Zero (At Least One Element of Any Format Is Not Zero)

__msa_bnz_wExperimentalMIPS-64 and msa

Immediate Branch If All Elements Are Not Zero

__msa_bsel_vExperimentalMIPS-64 and msa

Vector Bit Select

__msa_bseli_bExperimentalMIPS-64 and msa

Immediate Bit Select

__msa_bset_bExperimentalMIPS-64 and msa

Vector Bit Set

__msa_bset_dExperimentalMIPS-64 and msa

Vector Bit Set

__msa_bset_hExperimentalMIPS-64 and msa

Vector Bit Set

__msa_bset_wExperimentalMIPS-64 and msa

Vector Bit Set

__msa_bseti_bExperimentalMIPS-64 and msa

Immediate Bit Set

__msa_bseti_dExperimentalMIPS-64 and msa

Immediate Bit Set

__msa_bseti_hExperimentalMIPS-64 and msa

Immediate Bit Set

__msa_bseti_wExperimentalMIPS-64 and msa

Immediate Bit Set

__msa_bz_bExperimentalMIPS-64 and msa

Immediate Branch If At Least One Element Is Zero

__msa_bz_dExperimentalMIPS-64 and msa

Immediate Branch If At Least One Element Is Zero

__msa_bz_hExperimentalMIPS-64 and msa

Immediate Branch If At Least One Element Is Zero

__msa_bz_vExperimentalMIPS-64 and msa

Immediate Branch If Zero (All Elements of Any Format Are Zero)

__msa_bz_wExperimentalMIPS-64 and msa

Immediate Branch If At Least One Element Is Zero

__msa_ceq_bExperimentalMIPS-64 and msa

Vector Compare Equal

__msa_ceq_dExperimentalMIPS-64 and msa

Vector Compare Equal

__msa_ceq_hExperimentalMIPS-64 and msa

Vector Compare Equal

__msa_ceq_wExperimentalMIPS-64 and msa

Vector Compare Equal

__msa_ceqi_bExperimentalMIPS-64 and msa

Immediate Compare Equal

__msa_ceqi_dExperimentalMIPS-64 and msa

Immediate Compare Equal

__msa_ceqi_hExperimentalMIPS-64 and msa

Immediate Compare Equal

__msa_ceqi_wExperimentalMIPS-64 and msa

Immediate Compare Equal

__msa_cfcmsaExperimentalMIPS-64 and msa

GPR Copy from MSA Control Register

__msa_cle_s_bExperimentalMIPS-64 and msa

Vector Compare Signed Less Than or Equal

__msa_cle_s_dExperimentalMIPS-64 and msa

Vector Compare Signed Less Than or Equal

__msa_cle_s_hExperimentalMIPS-64 and msa

Vector Compare Signed Less Than or Equal

__msa_cle_s_wExperimentalMIPS-64 and msa

Vector Compare Signed Less Than or Equal

__msa_cle_u_bExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than or Equal

__msa_cle_u_dExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than or Equal

__msa_cle_u_hExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than or Equal

__msa_cle_u_wExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than or Equal

__msa_clei_s_bExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than or Equal

__msa_clei_s_dExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than or Equal

__msa_clei_s_hExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than or Equal

__msa_clei_s_wExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than or Equal

__msa_clei_u_bExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than or Equal

__msa_clei_u_dExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than or Equal

__msa_clei_u_hExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than or Equal

__msa_clei_u_wExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than or Equal

__msa_clt_s_bExperimentalMIPS-64 and msa

Vector Compare Signed Less Than

__msa_clt_s_dExperimentalMIPS-64 and msa

Vector Compare Signed Less Than

__msa_clt_s_hExperimentalMIPS-64 and msa

Vector Compare Signed Less Than

__msa_clt_s_wExperimentalMIPS-64 and msa

Vector Compare Signed Less Than

__msa_clt_u_bExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than

__msa_clt_u_dExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than

__msa_clt_u_hExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than

__msa_clt_u_wExperimentalMIPS-64 and msa

Vector Compare Unsigned Less Than

__msa_clti_s_bExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than

__msa_clti_s_dExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than

__msa_clti_s_hExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than

__msa_clti_s_wExperimentalMIPS-64 and msa

Immediate Compare Signed Less Than

__msa_clti_u_bExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than

__msa_clti_u_dExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than

__msa_clti_u_hExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than

__msa_clti_u_wExperimentalMIPS-64 and msa

Immediate Compare Unsigned Less Than

__msa_copy_s_bExperimentalMIPS-64 and msa

Element Copy to GPR Signed

__msa_copy_s_dExperimentalMIPS-64 and msa

Element Copy to GPR Signed

__msa_copy_s_hExperimentalMIPS-64 and msa

Element Copy to GPR Signed

__msa_copy_s_wExperimentalMIPS-64 and msa

Element Copy to GPR Signed

__msa_copy_u_bExperimentalMIPS-64 and msa

Element Copy to GPR Unsigned

__msa_copy_u_dExperimentalMIPS-64 and msa

Element Copy to GPR Unsigned

__msa_copy_u_hExperimentalMIPS-64 and msa

Element Copy to GPR Unsigned

__msa_copy_u_wExperimentalMIPS-64 and msa

Element Copy to GPR Unsigned

__msa_ctcmsaExperimentalMIPS-64 and msa

GPR Copy to MSA Control Register The content of the least significant 31 bits of GPR imm1 is copied to MSA control register cd Can not be tested in user mode

__msa_div_s_bExperimentalMIPS-64 and msa

Vector Signed Divide

__msa_div_s_dExperimentalMIPS-64 and msa

Vector Signed Divide

__msa_div_s_hExperimentalMIPS-64 and msa

Vector Signed Divide

__msa_div_s_wExperimentalMIPS-64 and msa

Vector Signed Divide

__msa_div_u_bExperimentalMIPS-64 and msa

Vector Unsigned Divide

__msa_div_u_dExperimentalMIPS-64 and msa

Vector Unsigned Divide

__msa_div_u_hExperimentalMIPS-64 and msa

Vector Unsigned Divide

__msa_div_u_wExperimentalMIPS-64 and msa

Vector Unsigned Divide

__msa_dotp_s_dExperimentalMIPS-64 and msa

Vector Signed Dot Product

__msa_dotp_s_hExperimentalMIPS-64 and msa

Vector Signed Dot Product

__msa_dotp_s_wExperimentalMIPS-64 and msa

Vector Signed Dot Product

__msa_dotp_u_dExperimentalMIPS-64 and msa

Vector Unsigned Dot Product

__msa_dotp_u_hExperimentalMIPS-64 and msa

Vector Unsigned Dot Product

__msa_dotp_u_wExperimentalMIPS-64 and msa

Vector Unsigned Dot Product

__msa_dpadd_s_dExperimentalMIPS-64 and msa

Vector Signed Dot Product and Add

__msa_dpadd_s_hExperimentalMIPS-64 and msa

Vector Signed Dot Product and Add

__msa_dpadd_s_wExperimentalMIPS-64 and msa

Vector Signed Dot Product and Add

__msa_dpadd_u_dExperimentalMIPS-64 and msa

Vector Unsigned Dot Product and Add

__msa_dpadd_u_hExperimentalMIPS-64 and msa

Vector Unsigned Dot Product and Add

__msa_dpadd_u_wExperimentalMIPS-64 and msa

Vector Unsigned Dot Product and Add

__msa_dpsub_s_dExperimentalMIPS-64 and msa

Vector Signed Dot Product and Add

__msa_dpsub_s_hExperimentalMIPS-64 and msa

Vector Signed Dot Product and Add

__msa_dpsub_s_wExperimentalMIPS-64 and msa

Vector Signed Dot Product and Add

__msa_dpsub_u_dExperimentalMIPS-64 and msa

Vector Unsigned Dot Product and Add

__msa_dpsub_u_hExperimentalMIPS-64 and msa

Vector Unsigned Dot Product and Add

__msa_dpsub_u_wExperimentalMIPS-64 and msa

Vector Unsigned Dot Product and Add

__msa_fadd_dExperimentalMIPS-64 and msa

Vector Floating-Point Addition

__msa_fadd_wExperimentalMIPS-64 and msa

Vector Floating-Point Addition

__msa_fcaf_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Always False

__msa_fcaf_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Always False

__msa_fceq_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Equal

__msa_fceq_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Equal

__msa_fclass_dExperimentalMIPS-64 and msa

Vector Floating-Point Class Mask

__msa_fclass_wExperimentalMIPS-64 and msa

Vector Floating-Point Class Mask

__msa_fcle_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Less or Equal

__msa_fcle_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Less or Equal

__msa_fclt_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Less Than

__msa_fclt_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Less Than

__msa_fcne_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Not Equal

__msa_fcne_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Not Equal

__msa_fcor_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Ordered

__msa_fcor_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Ordered

__msa_fcueq_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Equal

__msa_fcueq_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Equal

__msa_fcule_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Less or Equal

__msa_fcule_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Less or Equal

__msa_fcult_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Less Than

__msa_fcult_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Less Than

__msa_fcun_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered

__msa_fcun_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered

__msa_fcune_dExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Not Equal

__msa_fcune_wExperimentalMIPS-64 and msa

Vector Floating-Point Quiet Compare Unordered or Not Equal

__msa_fdiv_dExperimentalMIPS-64 and msa

Vector Floating-Point Division

__msa_fdiv_wExperimentalMIPS-64 and msa

Vector Floating-Point Division

__msa_fexdo_wExperimentalMIPS-64 and msa

Vector Floating-Point Down-Convert Interchange Format

__msa_fexp2_wExperimentalMIPS-64 and msa

Vector Floating-Point Down-Convert Interchange Format

__msa_fexp2_dExperimentalMIPS-64 and msa

Vector Floating-Point Down-Convert Interchange Format

__msa_fexupl_dExperimentalMIPS-64 and msa

Vector Floating-Point Up-Convert Interchange Format Left

__msa_fexupr_dExperimentalMIPS-64 and msa

Vector Floating-Point Up-Convert Interchange Format Left

__msa_ffint_s_dExperimentalMIPS-64 and msa

Vector Floating-Point Round and Convert from Signed Integer

__msa_ffint_s_wExperimentalMIPS-64 and msa

Vector Floating-Point Round and Convert from Signed Integer

__msa_ffint_u_dExperimentalMIPS-64 and msa

Vector Floating-Point Round and Convert from Unsigned Integer

__msa_ffint_u_wExperimentalMIPS-64 and msa

Vector Floating-Point Round and Convert from Unsigned Integer

__msa_ffql_dExperimentalMIPS-64 and msa

Vector Floating-Point Convert from Fixed-Point Left

__msa_ffql_wExperimentalMIPS-64 and msa

Vector Floating-Point Convert from Fixed-Point Left

__msa_ffqr_dExperimentalMIPS-64 and msa

Vector Floating-Point Convert from Fixed-Point Left

__msa_ffqr_wExperimentalMIPS-64 and msa

Vector Floating-Point Convert from Fixed-Point Left

__msa_fill_bExperimentalMIPS-64 and msa

Vector Fill from GPR

__msa_fill_dExperimentalMIPS-64 and msa

Vector Fill from GPR

__msa_fill_hExperimentalMIPS-64 and msa

Vector Fill from GPR

__msa_fill_wExperimentalMIPS-64 and msa

Vector Fill from GPR

__msa_flog2_wExperimentalMIPS-64 and msa

Vector Floating-Point Base 2 Logarithm

__msa_flog2_dExperimentalMIPS-64 and msa

Vector Floating-Point Base 2 Logarithm

__msa_fmadd_dExperimentalMIPS-64 and msa

Vector Floating-Point Multiply-Add

__msa_fmadd_wExperimentalMIPS-64 and msa

Vector Floating-Point Multiply-Add

__msa_fmax_a_dExperimentalMIPS-64 and msa

Vector Floating-Point Maximum Based on Absolute Values

__msa_fmax_a_wExperimentalMIPS-64 and msa

Vector Floating-Point Maximum Based on Absolute Values

__msa_fmax_dExperimentalMIPS-64 and msa

Vector Floating-Point Maximum

__msa_fmax_wExperimentalMIPS-64 and msa

Vector Floating-Point Maximum

__msa_fmin_a_dExperimentalMIPS-64 and msa

Vector Floating-Point Minimum Based on Absolute Values

__msa_fmin_a_wExperimentalMIPS-64 and msa

Vector Floating-Point Minimum Based on Absolute Values

__msa_fmin_dExperimentalMIPS-64 and msa

Vector Floating-Point Minimum

__msa_fmin_wExperimentalMIPS-64 and msa

Vector Floating-Point Minimum

__msa_fmsub_dExperimentalMIPS-64 and msa

Vector Floating-Point Multiply-Sub

__msa_fmsub_wExperimentalMIPS-64 and msa

Vector Floating-Point Multiply-Sub

__msa_fmul_dExperimentalMIPS-64 and msa

Vector Floating-Point Multiplication

__msa_fmul_wExperimentalMIPS-64 and msa

Vector Floating-Point Multiplication

__msa_frcp_dExperimentalMIPS-64 and msa

Vector Approximate Floating-Point Reciprocal

__msa_frcp_wExperimentalMIPS-64 and msa

Vector Approximate Floating-Point Reciprocal

__msa_frint_dExperimentalMIPS-64 and msa

Vector Floating-Point Round to Integer

__msa_frint_wExperimentalMIPS-64 and msa

Vector Floating-Point Round to Integer

__msa_frsqrt_dExperimentalMIPS-64 and msa

Vector Approximate Floating-Point Reciprocal of Square Root

__msa_frsqrt_wExperimentalMIPS-64 and msa

Vector Approximate Floating-Point Reciprocal of Square Root

__msa_fsaf_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Always False

__msa_fsaf_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Always False

__msa_fseq_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Equal

__msa_fseq_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Equal

__msa_fsle_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Less or Equal

__msa_fsle_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Less or Equal

__msa_fslt_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Less Than

__msa_fslt_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Less Than

__msa_fsne_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Not Equal

__msa_fsne_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Not Equal

__msa_fsor_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Ordered

__msa_fsor_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Ordered

__msa_fsqrt_dExperimentalMIPS-64 and msa

Vector Floating-Point Square Root

__msa_fsqrt_wExperimentalMIPS-64 and msa

Vector Floating-Point Square Root

__msa_fsub_dExperimentalMIPS-64 and msa

Vector Floating-Point Subtraction

__msa_fsub_wExperimentalMIPS-64 and msa

Vector Floating-Point Subtraction

__msa_fsueq_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Ordered

__msa_fsueq_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Ordered

__msa_fsule_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered or Less or Equal

__msa_fsule_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered or Less or Equal

__msa_fsult_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered or Less Than

__msa_fsult_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered or Less Than

__msa_fsun_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered

__msa_fsun_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered

__msa_fsune_dExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered or Not Equal

__msa_fsune_wExperimentalMIPS-64 and msa

Vector Floating-Point Signaling Compare Unordered or Not Equal

__msa_ftint_s_dExperimentalMIPS-64 and msa

Vector Floating-Point Convert to Signed Integer

__msa_ftint_s_wExperimentalMIPS-64 and msa

Vector Floating-Point Convert to Signed Integer

__msa_ftint_u_dExperimentalMIPS-64 and msa

Vector Floating-Point Convert to Unsigned Integer

__msa_ftint_u_wExperimentalMIPS-64 and msa

Vector Floating-Point Convert to Unsigned Integer

__msa_ftq_hExperimentalMIPS-64 and msa

Vector Floating-Point Convert to Fixed-Point

__msa_ftq_wExperimentalMIPS-64 and msa

Vector Floating-Point Convert to Fixed-Point

__msa_ftrunc_s_dExperimentalMIPS-64 and msa

Vector Floating-Point Truncate and Convert to Signed Integer

__msa_ftrunc_s_wExperimentalMIPS-64 and msa

Vector Floating-Point Truncate and Convert to Signed Integer

__msa_ftrunc_u_dExperimentalMIPS-64 and msa

Vector Floating-Point Truncate and Convert to Unsigned Integer

__msa_ftrunc_u_wExperimentalMIPS-64 and msa

Vector Floating-Point Truncate and Convert to Unsigned Integer

__msa_hadd_s_dExperimentalMIPS-64 and msa

Vector Signed Horizontal Add

__msa_hadd_s_hExperimentalMIPS-64 and msa

Vector Signed Horizontal Add

__msa_hadd_s_wExperimentalMIPS-64 and msa

Vector Signed Horizontal Add

__msa_hadd_u_dExperimentalMIPS-64 and msa

Vector Unsigned Horizontal Add

__msa_hadd_u_hExperimentalMIPS-64 and msa

Vector Unsigned Horizontal Add

__msa_hadd_u_wExperimentalMIPS-64 and msa

Vector Unsigned Horizontal Add

__msa_hsub_s_dExperimentalMIPS-64 and msa

Vector Signed Horizontal Subtract

__msa_hsub_s_hExperimentalMIPS-64 and msa

Vector Signed Horizontal Subtract

__msa_hsub_s_wExperimentalMIPS-64 and msa

Vector Signed Horizontal Subtract

__msa_hsub_u_dExperimentalMIPS-64 and msa

Vector Unsigned Horizontal Subtract

__msa_hsub_u_hExperimentalMIPS-64 and msa

Vector Unsigned Horizontal Subtract

__msa_hsub_u_wExperimentalMIPS-64 and msa

Vector Unsigned Horizontal Subtract

__msa_ilvev_bExperimentalMIPS-64 and msa

Vector Interleave Even

__msa_ilvev_dExperimentalMIPS-64 and msa

Vector Interleave Even

__msa_ilvev_hExperimentalMIPS-64 and msa

Vector Interleave Even

__msa_ilvev_wExperimentalMIPS-64 and msa

Vector Interleave Even

__msa_ilvl_bExperimentalMIPS-64 and msa

Vector Interleave Left

__msa_ilvl_dExperimentalMIPS-64 and msa

Vector Interleave Left

__msa_ilvl_hExperimentalMIPS-64 and msa

Vector Interleave Left

__msa_ilvl_wExperimentalMIPS-64 and msa

Vector Interleave Left

__msa_ilvod_bExperimentalMIPS-64 and msa

Vector Interleave Odd

__msa_ilvod_dExperimentalMIPS-64 and msa

Vector Interleave Odd

__msa_ilvod_hExperimentalMIPS-64 and msa

Vector Interleave Odd

__msa_ilvod_wExperimentalMIPS-64 and msa

Vector Interleave Odd

__msa_ilvr_bExperimentalMIPS-64 and msa

Vector Interleave Right

__msa_ilvr_dExperimentalMIPS-64 and msa

Vector Interleave Right

__msa_ilvr_hExperimentalMIPS-64 and msa

Vector Interleave Right

__msa_ilvr_wExperimentalMIPS-64 and msa

Vector Interleave Right

__msa_insert_bExperimentalMIPS-64 and msa

GPR Insert Element

__msa_insert_dExperimentalMIPS-64 and msa

GPR Insert Element

__msa_insert_hExperimentalMIPS-64 and msa

GPR Insert Element

__msa_insert_wExperimentalMIPS-64 and msa

GPR Insert Element

__msa_insve_bExperimentalMIPS-64 and msa

Element Insert Element

__msa_insve_dExperimentalMIPS-64 and msa

Element Insert Element

__msa_insve_hExperimentalMIPS-64 and msa

Element Insert Element

__msa_insve_wExperimentalMIPS-64 and msa

Element Insert Element

__msa_ld_bExperimentalMIPS-64 and msa

Vector Load

__msa_ld_dExperimentalMIPS-64 and msa

Vector Load

__msa_ld_hExperimentalMIPS-64 and msa

Vector Load

__msa_ld_wExperimentalMIPS-64 and msa

Vector Load

__msa_ldi_bExperimentalMIPS-64 and msa

Immediate Load

__msa_ldi_dExperimentalMIPS-64 and msa

Immediate Load

__msa_ldi_hExperimentalMIPS-64 and msa

Immediate Load

__msa_ldi_wExperimentalMIPS-64 and msa

Immediate Load

__msa_madd_q_hExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Add

__msa_madd_q_wExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Add

__msa_maddr_q_hExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Add Rounded

__msa_maddr_q_wExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Add Rounded

__msa_maddv_bExperimentalMIPS-64 and msa

Vector Multiply and Add

__msa_maddv_dExperimentalMIPS-64 and msa

Vector Multiply and Add

__msa_maddv_hExperimentalMIPS-64 and msa

Vector Multiply and Add

__msa_maddv_wExperimentalMIPS-64 and msa

Vector Multiply and Add

__msa_max_a_bExperimentalMIPS-64 and msa

Vector Maximum Based on Absolute Values

__msa_max_a_dExperimentalMIPS-64 and msa

Vector Maximum Based on Absolute Values

__msa_max_a_hExperimentalMIPS-64 and msa

Vector Maximum Based on Absolute Values

__msa_max_a_wExperimentalMIPS-64 and msa

Vector Maximum Based on Absolute Values

__msa_max_s_bExperimentalMIPS-64 and msa

Vector Signed Maximum

__msa_max_s_dExperimentalMIPS-64 and msa

Vector Signed Maximum

__msa_max_s_hExperimentalMIPS-64 and msa

Vector Signed Maximum

__msa_max_s_wExperimentalMIPS-64 and msa

Vector Signed Maximum

__msa_max_u_bExperimentalMIPS-64 and msa

Vector Unsigned Maximum

__msa_max_u_dExperimentalMIPS-64 and msa

Vector Unsigned Maximum

__msa_max_u_hExperimentalMIPS-64 and msa

Vector Unsigned Maximum

__msa_max_u_wExperimentalMIPS-64 and msa

Vector Unsigned Maximum

__msa_maxi_s_bExperimentalMIPS-64 and msa

Immediate Signed Maximum

__msa_maxi_s_dExperimentalMIPS-64 and msa

Immediate Signed Maximum

__msa_maxi_s_hExperimentalMIPS-64 and msa

Immediate Signed Maximum

__msa_maxi_s_wExperimentalMIPS-64 and msa

Immediate Signed Maximum

__msa_maxi_u_bExperimentalMIPS-64 and msa

Immediate Unsigned Maximum

__msa_maxi_u_dExperimentalMIPS-64 and msa

Immediate Unsigned Maximum

__msa_maxi_u_hExperimentalMIPS-64 and msa

Immediate Unsigned Maximum

__msa_maxi_u_wExperimentalMIPS-64 and msa

Immediate Unsigned Maximum

__msa_min_a_bExperimentalMIPS-64 and msa

Vector Minimum Based on Absolute Value

__msa_min_a_dExperimentalMIPS-64 and msa

Vector Minimum Based on Absolute Value

__msa_min_a_hExperimentalMIPS-64 and msa

Vector Minimum Based on Absolute Value

__msa_min_a_wExperimentalMIPS-64 and msa

Vector Minimum Based on Absolute Value

__msa_min_s_bExperimentalMIPS-64 and msa

Vector Signed Minimum

__msa_min_s_dExperimentalMIPS-64 and msa

Vector Signed Minimum

__msa_min_s_hExperimentalMIPS-64 and msa

Vector Signed Minimum

__msa_min_s_wExperimentalMIPS-64 and msa

Vector Signed Minimum

__msa_min_u_bExperimentalMIPS-64 and msa

Vector Unsigned Minimum

__msa_min_u_dExperimentalMIPS-64 and msa

Vector Unsigned Minimum

__msa_min_u_hExperimentalMIPS-64 and msa

Vector Unsigned Minimum

__msa_min_u_wExperimentalMIPS-64 and msa

Vector Unsigned Minimum

__msa_mini_s_bExperimentalMIPS-64 and msa

Immediate Signed Minimum

__msa_mini_s_dExperimentalMIPS-64 and msa

Immediate Signed Minimum

__msa_mini_s_hExperimentalMIPS-64 and msa

Immediate Signed Minimum

__msa_mini_s_wExperimentalMIPS-64 and msa

Immediate Signed Minimum

__msa_mini_u_bExperimentalMIPS-64 and msa

Immediate Unsigned Minimum

__msa_mini_u_dExperimentalMIPS-64 and msa

Immediate Unsigned Minimum

__msa_mini_u_hExperimentalMIPS-64 and msa

Immediate Unsigned Minimum

__msa_mini_u_wExperimentalMIPS-64 and msa

Immediate Unsigned Minimum

__msa_mod_s_bExperimentalMIPS-64 and msa

Vector Signed Modulo

__msa_mod_s_dExperimentalMIPS-64 and msa

Vector Signed Modulo

__msa_mod_s_hExperimentalMIPS-64 and msa

Vector Signed Modulo

__msa_mod_s_wExperimentalMIPS-64 and msa

Vector Signed Modulo

__msa_mod_u_bExperimentalMIPS-64 and msa

Vector Unsigned Modulo

__msa_mod_u_dExperimentalMIPS-64 and msa

Vector Unsigned Modulo

__msa_mod_u_hExperimentalMIPS-64 and msa

Vector Unsigned Modulo

__msa_mod_u_wExperimentalMIPS-64 and msa

Vector Unsigned Modulo

__msa_move_vExperimentalMIPS-64 and msa

Vector Move

__msa_msub_q_hExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Subtract

__msa_msub_q_wExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Subtract

__msa_msubr_q_hExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Subtract Rounded

__msa_msubr_q_wExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply and Subtract Rounded

__msa_msubv_bExperimentalMIPS-64 and msa

Vector Multiply and Subtract

__msa_msubv_dExperimentalMIPS-64 and msa

Vector Multiply and Subtract

__msa_msubv_hExperimentalMIPS-64 and msa

Vector Multiply and Subtract

__msa_msubv_wExperimentalMIPS-64 and msa

Vector Multiply and Subtract

__msa_mul_q_hExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply

__msa_mul_q_wExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply

__msa_mulr_q_hExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply Rounded

__msa_mulr_q_wExperimentalMIPS-64 and msa

Vector Fixed-Point Multiply Rounded

__msa_mulv_bExperimentalMIPS-64 and msa

Vector Multiply

__msa_mulv_dExperimentalMIPS-64 and msa

Vector Multiply

__msa_mulv_hExperimentalMIPS-64 and msa

Vector Multiply

__msa_mulv_wExperimentalMIPS-64 and msa

Vector Multiply

__msa_nloc_bExperimentalMIPS-64 and msa

Vector Leading Ones Count

__msa_nloc_dExperimentalMIPS-64 and msa

Vector Leading Ones Count

__msa_nloc_hExperimentalMIPS-64 and msa

Vector Leading Ones Count

__msa_nloc_wExperimentalMIPS-64 and msa

Vector Leading Ones Count

__msa_nlzc_bExperimentalMIPS-64 and msa

Vector Leading Zeros Count

__msa_nlzc_dExperimentalMIPS-64 and msa

Vector Leading Zeros Count

__msa_nlzc_hExperimentalMIPS-64 and msa

Vector Leading Zeros Count

__msa_nlzc_wExperimentalMIPS-64 and msa

Vector Leading Zeros Count

__msa_nor_vExperimentalMIPS-64 and msa

Vector Logical Negated Or

__msa_nori_bExperimentalMIPS-64 and msa

Immediate Logical Negated Or

__msa_or_vExperimentalMIPS-64 and msa

Vector Logical Or

__msa_ori_bExperimentalMIPS-64 and msa

Immediate Logical Or

__msa_pckev_bExperimentalMIPS-64 and msa

Vector Pack Even

__msa_pckev_dExperimentalMIPS-64 and msa

Vector Pack Even

__msa_pckev_hExperimentalMIPS-64 and msa

Vector Pack Even

__msa_pckev_wExperimentalMIPS-64 and msa

Vector Pack Even

__msa_pckod_bExperimentalMIPS-64 and msa

Vector Pack Odd

__msa_pckod_dExperimentalMIPS-64 and msa

Vector Pack Odd

__msa_pckod_hExperimentalMIPS-64 and msa

Vector Pack Odd

__msa_pckod_wExperimentalMIPS-64 and msa

Vector Pack Odd

__msa_pcnt_bExperimentalMIPS-64 and msa

Vector Population Count

__msa_pcnt_dExperimentalMIPS-64 and msa

Vector Population Count

__msa_pcnt_hExperimentalMIPS-64 and msa

Vector Population Count

__msa_pcnt_wExperimentalMIPS-64 and msa

Vector Population Count

__msa_sat_s_bExperimentalMIPS-64 and msa

Immediate Signed Saturate

__msa_sat_s_dExperimentalMIPS-64 and msa

Immediate Signed Saturate

__msa_sat_s_hExperimentalMIPS-64 and msa

Immediate Signed Saturate

__msa_sat_s_wExperimentalMIPS-64 and msa

Immediate Signed Saturate

__msa_sat_u_bExperimentalMIPS-64 and msa

Immediate Unsigned Saturate

__msa_sat_u_dExperimentalMIPS-64 and msa

Immediate Unsigned Saturate

__msa_sat_u_hExperimentalMIPS-64 and msa

Immediate Unsigned Saturate

__msa_sat_u_wExperimentalMIPS-64 and msa

Immediate Unsigned Saturate

__msa_shf_bExperimentalMIPS-64 and msa

Immediate Set Shuffle Elements

__msa_shf_hExperimentalMIPS-64 and msa

Immediate Set Shuffle Elements

__msa_shf_wExperimentalMIPS-64 and msa

Immediate Set Shuffle Elements

__msa_sld_bExperimentalMIPS-64 and msa

GPR Columns Slide

__msa_sld_dExperimentalMIPS-64 and msa

GPR Columns Slide

__msa_sld_hExperimentalMIPS-64 and msa

GPR Columns Slide

__msa_sld_wExperimentalMIPS-64 and msa

GPR Columns Slide

__msa_sldi_bExperimentalMIPS-64 and msa

Immediate Columns Slide

__msa_sldi_dExperimentalMIPS-64 and msa

Immediate Columns Slide

__msa_sldi_hExperimentalMIPS-64 and msa

Immediate Columns Slide

__msa_sldi_wExperimentalMIPS-64 and msa

Immediate Columns Slide

__msa_sll_bExperimentalMIPS-64 and msa

Vector Shift Left

__msa_sll_dExperimentalMIPS-64 and msa

Vector Shift Left

__msa_sll_hExperimentalMIPS-64 and msa

Vector Shift Left

__msa_sll_wExperimentalMIPS-64 and msa

Vector Shift Left

__msa_slli_bExperimentalMIPS-64 and msa

Immediate Shift Left

__msa_slli_dExperimentalMIPS-64 and msa

Immediate Shift Left

__msa_slli_hExperimentalMIPS-64 and msa

Immediate Shift Left

__msa_slli_wExperimentalMIPS-64 and msa

Immediate Shift Left

__msa_splat_bExperimentalMIPS-64 and msa

GPR Element Splat

__msa_splat_dExperimentalMIPS-64 and msa

GPR Element Splat

__msa_splat_hExperimentalMIPS-64 and msa

GPR Element Splat

__msa_splat_wExperimentalMIPS-64 and msa

GPR Element Splat

__msa_splati_bExperimentalMIPS-64 and msa

Immediate Element Splat

__msa_splati_dExperimentalMIPS-64 and msa

Immediate Element Splat

__msa_splati_hExperimentalMIPS-64 and msa

Immediate Element Splat

__msa_splati_wExperimentalMIPS-64 and msa

Immediate Element Splat

__msa_sra_bExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic

__msa_sra_dExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic

__msa_sra_hExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic

__msa_sra_wExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic

__msa_srai_bExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic

__msa_srai_dExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic

__msa_srai_hExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic

__msa_srai_wExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic

__msa_srar_bExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic Rounded

__msa_srar_dExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic Rounded

__msa_srar_hExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic Rounded

__msa_srar_wExperimentalMIPS-64 and msa

Vector Shift Right Arithmetic Rounded

__msa_srari_bExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic Rounded

__msa_srari_dExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic Rounded

__msa_srari_hExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic Rounded

__msa_srari_wExperimentalMIPS-64 and msa

Immediate Shift Right Arithmetic Rounded

__msa_srl_bExperimentalMIPS-64 and msa

Vector Shift Right Logical

__msa_srl_dExperimentalMIPS-64 and msa

Vector Shift Right Logical

__msa_srl_hExperimentalMIPS-64 and msa

Vector Shift Right Logical

__msa_srl_wExperimentalMIPS-64 and msa

Vector Shift Right Logical

__msa_srli_bExperimentalMIPS-64 and msa

Immediate Shift Right Logical

__msa_srli_dExperimentalMIPS-64 and msa

Immediate Shift Right Logical

__msa_srli_hExperimentalMIPS-64 and msa

Immediate Shift Right Logical

__msa_srli_wExperimentalMIPS-64 and msa

Immediate Shift Right Logical

__msa_srlr_bExperimentalMIPS-64 and msa

Vector Shift Right Logical Rounded

__msa_srlr_dExperimentalMIPS-64 and msa

Vector Shift Right Logical Rounded

__msa_srlr_hExperimentalMIPS-64 and msa

Vector Shift Right Logical Rounded

__msa_srlr_wExperimentalMIPS-64 and msa

Vector Shift Right Logical Rounded

__msa_srlri_bExperimentalMIPS-64 and msa

Immediate Shift Right Logical Rounded

__msa_srlri_dExperimentalMIPS-64 and msa

Immediate Shift Right Logical Rounded

__msa_srlri_hExperimentalMIPS-64 and msa

Immediate Shift Right Logical Rounded

__msa_srlri_wExperimentalMIPS-64 and msa

Immediate Shift Right Logical Rounded

__msa_st_bExperimentalMIPS-64 and msa

Vector Store

__msa_st_dExperimentalMIPS-64 and msa

Vector Store

__msa_st_hExperimentalMIPS-64 and msa

Vector Store

__msa_st_wExperimentalMIPS-64 and msa

Vector Store

__msa_subs_s_bExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Signed Values

__msa_subs_s_dExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Signed Values

__msa_subs_s_hExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Signed Values

__msa_subs_s_wExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Signed Values

__msa_subs_u_bExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Unsigned Values

__msa_subs_u_dExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Unsigned Values

__msa_subs_u_hExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Unsigned Values

__msa_subs_u_wExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Unsigned Values

__msa_subsus_u_bExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Signed from Unsigned

__msa_subsus_u_dExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Signed from Unsigned

__msa_subsus_u_hExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Signed from Unsigned

__msa_subsus_u_wExperimentalMIPS-64 and msa

Vector Unsigned Saturated Subtract of Signed from Unsigned

__msa_subsuu_s_bExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Unsigned Values

__msa_subsuu_s_dExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Unsigned Values

__msa_subsuu_s_hExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Unsigned Values

__msa_subsuu_s_wExperimentalMIPS-64 and msa

Vector Signed Saturated Subtract of Unsigned Values

__msa_subv_bExperimentalMIPS-64 and msa

Vector Subtract

__msa_subv_dExperimentalMIPS-64 and msa

Vector Subtract

__msa_subv_hExperimentalMIPS-64 and msa

Vector Subtract

__msa_subv_wExperimentalMIPS-64 and msa

Vector Subtract

__msa_subvi_bExperimentalMIPS-64 and msa

Immediate Subtract

__msa_subvi_dExperimentalMIPS-64 and msa

Immediate Subtract

__msa_subvi_hExperimentalMIPS-64 and msa

Immediate Subtract

__msa_subvi_wExperimentalMIPS-64 and msa

Immediate Subtract

__msa_vshf_bExperimentalMIPS-64 and msa

Vector Data Preserving Shuffle

__msa_vshf_dExperimentalMIPS-64 and msa

Vector Data Preserving Shuffle

__msa_vshf_hExperimentalMIPS-64 and msa

Vector Data Preserving Shuffle

__msa_vshf_wExperimentalMIPS-64 and msa

Vector Data Preserving Shuffle

__msa_xor_vExperimentalMIPS-64 and msa

Vector Logical Exclusive Or

__msa_xori_bExperimentalMIPS-64 and msa

Immediate Logical Exclusive Or

break_ExperimentalMIPS-64

Generates the trap instruction BREAK