[−][src]Function core::arch::mips64::__msa_ilvr_w
pub unsafe fn __msa_ilvr_w(a: v4i32, b: v4i32) -> v4i32
This is supported on MIPS-64 and target feature
msa only.Vector Interleave Right
The right half elements in vectors 'a' (four signed 32-bit integer numbers) and vector 'b' (four signed 32-bit integer numbers) are copied to the result (four signed 32-bit integer numbers) alternating one element from 'a' with one element from 'b'.