[−][src]Function core::arch::mips64::__msa_aver_s_w
pub unsafe fn __msa_aver_s_w(a: v4i32, b: v4i32) -> v4i32
This is supported on MIPS-64 and target feature
msa only.Vector Signed Average Rounded
The elements in vector a (four signed 32-bit integer numbers)
are added to the elements in vector b (four signed 32-bit integer numbers)
The addition of the elements plus 1 (for rounding) is done signed with full precision,
i.e. the result has one extra bit.
Signed division by 2 (or arithmetic shift right by one bit) is performed before
writing the result to vector (four signed 32-bit integer numbers).