1.33.0[][src]Module core::arch::wasm32

This is supported on WebAssembly only.

Platform-specific intrinsics for the wasm32 platform.

See the module documentation for more details.

Structs

v128ExperimentalWebAssembly

WASM-specific 128-bit wide SIMD vector type.

Functions

memory_growWebAssembly

Corresponding intrinsic to wasm's memory.grow instruction

memory_sizeWebAssembly

Corresponding intrinsic to wasm's memory.size instruction

unreachableWebAssembly

Generates the trap instruction UNREACHABLE

atomic_notifyExperimentalWebAssembly

Corresponding intrinsic to wasm's atomic.notify instruction

f32x4_splatExperimentalWebAssembly

Creates a vector with identical lanes.

f32x4_extract_laneExperimentalWebAssembly

Extracts a lane from a 128-bit vector interpreted as 4 packed f32 numbers.

f32x4_replace_laneExperimentalWebAssembly

Replaces a lane from a 128-bit vector interpreted as 4 packed f32 numbers.

f32x4_eqExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_neExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_ltExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_gtExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_leExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_geExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.

f32x4_absExperimentalWebAssembly

Calculates the absolute value of each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.

f32x4_negExperimentalWebAssembly

Negates each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.

f32x4_sqrtExperimentalWebAssembly

Calculates the square root of each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.

f32x4_addExperimentalWebAssembly

Adds pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_subExperimentalWebAssembly

Subtracts pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_mulExperimentalWebAssembly

Multiplies pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_divExperimentalWebAssembly

Divides pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_minExperimentalWebAssembly

Calculates the minimum of pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_maxExperimentalWebAssembly

Calculates the maximum of pairwise lanes of two 128-bit vectors interpreted as four 32-bit floating point numbers.

f32x4_convert_i32x4_sExperimentalWebAssembly

Converts a 128-bit vector interpreted as four 32-bit signed integers into a 128-bit vector of four 32-bit floating point numbers.

f32x4_convert_i32x4_uExperimentalWebAssembly

Converts a 128-bit vector interpreted as four 32-bit unsigned integers into a 128-bit vector of four 32-bit floating point numbers.

f64x2_splatExperimentalWebAssembly

Creates a vector with identical lanes.

f64x2_extract_laneExperimentalWebAssembly

Extracts lane from a 128-bit vector interpreted as 2 packed f64 numbers.

f64x2_replace_laneExperimentalWebAssembly

Replaces a lane from a 128-bit vector interpreted as 2 packed f64 numbers.

f64x2_eqExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_neExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_ltExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_gtExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_leExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_geExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.

f64x2_absExperimentalWebAssembly

Calculates the absolute value of each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.

f64x2_negExperimentalWebAssembly

Negates each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.

f64x2_sqrtExperimentalWebAssembly

Calculates the square root of each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.

f64x2_addExperimentalWebAssembly

Adds pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_subExperimentalWebAssembly

Subtracts pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_mulExperimentalWebAssembly

Multiplies pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_divExperimentalWebAssembly

Divides pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_minExperimentalWebAssembly

Calculates the minimum of pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_maxExperimentalWebAssembly

Calculates the maximum of pairwise lanes of two 128-bit vectors interpreted as two 64-bit floating point numbers.

f64x2_convert_s_i64x2ExperimentalWebAssembly

Converts a 128-bit vector interpreted as two 64-bit signed integers into a 128-bit vector of two 64-bit floating point numbers.

f64x2_convert_u_i64x2ExperimentalWebAssembly

Converts a 128-bit vector interpreted as two 64-bit unsigned integers into a 128-bit vector of two 64-bit floating point numbers.

i32_atomic_waitExperimentalWebAssembly

Corresponding intrinsic to wasm's i32.atomic.wait instruction

i64_atomic_waitExperimentalWebAssembly

Corresponding intrinsic to wasm's i64.atomic.wait instruction

i16x8_splatExperimentalWebAssembly

Creates a vector with identical lanes.

i16x8_extract_laneExperimentalWebAssembly

Extracts a lane from a 128-bit vector interpreted as 8 packed i16 numbers.

i16x8_replace_laneExperimentalWebAssembly

Replaces a lane from a 128-bit vector interpreted as 8 packed i16 numbers.

i16x8_eqExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit integers.

i16x8_neExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit integers.

i16x8_lt_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_lt_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_gt_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_gt_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_le_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_le_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_ge_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit signed integers.

i16x8_ge_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.

i16x8_negExperimentalWebAssembly

Negates a 128-bit vectors intepreted as eight 16-bit signed integers

i16x8_any_trueExperimentalWebAssembly

Returns 1 if any lane is nonzero or 0 if all lanes are zero.

i16x8_all_trueExperimentalWebAssembly

Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.

i16x8_shlExperimentalWebAssembly

Shifts each lane to the left by the specified number of bits.

i16x8_shr_sExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, sign extending.

i16x8_shr_uExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i16x8_addExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed eight 16-bit integers.

i16x8_add_saturate_sExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed eight 16-bit signed integers, saturating on overflow to i16::max_value().

i16x8_add_saturate_uExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed eight 16-bit unsigned integers, saturating on overflow to u16::max_value().

i16x8_subExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed eight 16-bit integers.

i16x8_sub_saturate_sExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed eight 16-bit signed integers, saturating on overflow to i16::min_value().

i16x8_sub_saturate_uExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed eight 16-bit unsigned integers, saturating on overflow to 0.

i16x8_mulExperimentalWebAssembly

Multiplies two 128-bit vectors as if they were two packed eight 16-bit signed integers.

i32x4_splatExperimentalWebAssembly

Creates a vector with identical lanes.

i32x4_extract_laneExperimentalWebAssembly

Extracts a lane from a 128-bit vector interpreted as 4 packed i32 numbers.

i32x4_replace_laneExperimentalWebAssembly

Replaces a lane from a 128-bit vector interpreted as 4 packed i32 numbers.

i32x4_eqExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit integers.

i32x4_neExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit integers.

i32x4_lt_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_lt_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_gt_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_gt_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_le_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_le_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_ge_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.

i32x4_ge_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.

i32x4_negExperimentalWebAssembly

Negates a 128-bit vectors intepreted as four 32-bit signed integers

i32x4_any_trueExperimentalWebAssembly

Returns 1 if any lane is nonzero or 0 if all lanes are zero.

i32x4_all_trueExperimentalWebAssembly

Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.

i32x4_shlExperimentalWebAssembly

Shifts each lane to the left by the specified number of bits.

i32x4_shr_sExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, sign extending.

i32x4_shr_uExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i32x4_addExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed four 32-bit integers.

i32x4_subExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed four 32-bit integers.

i32x4_mulExperimentalWebAssembly

Multiplies two 128-bit vectors as if they were two packed four 32-bit signed integers.

i32x4_trunc_s_f32x4_satExperimentalWebAssembly

Converts a 128-bit vector interpreted as four 32-bit floating point numbers into a 128-bit vector of four 32-bit signed integers.

i32x4_trunc_u_f32x4_satExperimentalWebAssembly

Converts a 128-bit vector interpreted as four 32-bit floating point numbers into a 128-bit vector of four 32-bit unsigned integers.

i64x2_splatExperimentalWebAssembly

Creates a vector with identical lanes.

i64x2_extract_laneExperimentalWebAssembly

Extracts a lane from a 128-bit vector interpreted as 2 packed i64 numbers.

i64x2_replace_laneExperimentalWebAssembly

Replaces a lane from a 128-bit vector interpreted as 2 packed i64 numbers.

i64x2_negExperimentalWebAssembly

Negates a 128-bit vectors intepreted as two 64-bit signed integers

i64x2_any_trueExperimentalWebAssembly

Returns 1 if any lane is nonzero or 0 if all lanes are zero.

i64x2_all_trueExperimentalWebAssembly

Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.

i64x2_shlExperimentalWebAssembly

Shifts each lane to the left by the specified number of bits.

i64x2_shr_sExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, sign extending.

i64x2_shr_uExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i64x2_addExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed two 64-bit integers.

i64x2_subExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed two 64-bit integers.

i64x2_trunc_s_f64x2_satExperimentalWebAssembly

Converts a 128-bit vector interpreted as two 64-bit floating point numbers into a 128-bit vector of two 64-bit signed integers.

i64x2_trunc_u_f64x2_satExperimentalWebAssembly

Converts a 128-bit vector interpreted as two 64-bit floating point numbers into a 128-bit vector of two 64-bit unsigned integers.

i8x16_splatExperimentalWebAssembly

Creates a vector with identical lanes.

i8x16_extract_laneExperimentalWebAssembly

Extracts a lane from a 128-bit vector interpreted as 16 packed i8 numbers.

i8x16_replace_laneExperimentalWebAssembly

Replaces a lane from a 128-bit vector interpreted as 16 packed i8 numbers.

i8x16_eqExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit integers.

i8x16_neExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit integers.

i8x16_lt_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_lt_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_gt_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_gt_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_le_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_le_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_ge_sExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.

i8x16_ge_uExperimentalWebAssembly

Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.

i8x16_negExperimentalWebAssembly

Negates a 128-bit vectors intepreted as sixteen 8-bit signed integers

i8x16_any_trueExperimentalWebAssembly

Returns 1 if any lane is nonzero or 0 if all lanes are zero.

i8x16_all_trueExperimentalWebAssembly

Returns 1 if all lanes are nonzero or 0 if any lane is nonzero.

i8x16_shlExperimentalWebAssembly

Shifts each lane to the left by the specified number of bits.

i8x16_shr_sExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, sign extending.

i8x16_shr_uExperimentalWebAssembly

Shifts each lane to the right by the specified number of bits, shifting in zeros.

i8x16_addExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed sixteen 8-bit integers.

i8x16_add_saturate_sExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed sixteen 8-bit signed integers, saturating on overflow to i8::max_value().

i8x16_add_saturate_uExperimentalWebAssembly

Adds two 128-bit vectors as if they were two packed sixteen 8-bit unsigned integers, saturating on overflow to u8::max_value().

i8x16_subExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit integers.

i8x16_sub_saturate_sExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit signed integers, saturating on overflow to i8::min_value().

i8x16_sub_saturate_uExperimentalWebAssembly

Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit unsigned integers, saturating on overflow to 0.

i8x16_mulExperimentalWebAssembly

Multiplies two 128-bit vectors as if they were two packed sixteen 8-bit signed integers.

v128_loadExperimentalWebAssembly

Loads a v128 vector from the given heap address.

v128_storeExperimentalWebAssembly

Stores a v128 vector to the given heap address.

v128_constExperimentalWebAssembly

Materializes a constant SIMD value from the immediate operands.

v128_notExperimentalWebAssembly

Flips each bit of the 128-bit input vector.

v128_andExperimentalWebAssembly

Performs a bitwise and of the two input 128-bit vectors, returning the resulting vector.

v128_orExperimentalWebAssembly

Performs a bitwise or of the two input 128-bit vectors, returning the resulting vector.

v128_xorExperimentalWebAssembly

Performs a bitwise xor of the two input 128-bit vectors, returning the resulting vector.

v128_bitselectExperimentalWebAssembly

Use the bitmask in c to select bits from v1 when 1 and v2 when 0.